1. Technical Field
The following embodiments generally relate to an apparatus and method for video coding and, more particularly, to an apparatus and method for performing rate-distortion optimization based on cost.
2. Description of the Related Art
The ITU-T/ISO/IEC Joint Collaborative Team on Video Coding (JCT-VC) has developed a High Efficiency Video Coding (HEVC) standard technology having encoding efficiency that is more than twice that of Advanced Video Codec (AVC)/H.264 while maintaining the same video quality. Further, ITU-T/ISO/IEC JCT-VC published the Final Draft International Standard (FDIS) on January, 2013 in relation to HEVC technology.
A large number of technologies have been added to HEVC technology in order to achieve high encoding performance Due to the addition of a large number of technologies, the complexity of an encoding apparatus using HEVC technology has greatly increased. Therefore, in order to utilize HEVC technology commercially, the encoding apparatus requires the improvement of an encoding speed based on the reduction of the complexity of the encoding apparatus.
In a typical video encoding apparatus, encoding based on a macroblock composed of 16×16 pixels is performed. In contrast, in an HEVC encoding apparatus, encoding is performed based on a Coding Tree Unit (CTU). A CTU may have a size of 64×64, 32×32, or 16×16. Typically, a CTU having a size of 64×64 is widely used. In the HEVC encoding apparatus, quadtree coding based on a CTU is performed. The CTU has the shape of a quadtree and is divided into coding units (CUs). In other words, a CU may be a block in a CTU. In the HEVC encoding apparatus, prediction and transform are performed based on CUs. Such a CU may have a size of 64×64, 32×32, 16×16 or 8×8. Further, the CU is configured to minimize Rate-Distortion Cost (RDC) while having a quadtree structure in the CTU.
To achieve the purpose of encoding and improve the efficiency of the encoding apparatus, a conventional HEVC encoding apparatus may calculate rate-distortion costs for 1) quadtree coding based on CTU, 2) the size of each block based on quadtree coding, and 3) the encoding mode of each block, and may determine quadtree coding and the encoding mode of the block depending on the calculated rate-distortion costs. Here, the encoding modes may include a skip mode, a merge mode, an inter mode, and an intra mode. Further, the HEVC encoding apparatus is configured to naturally perform a motion compensation step while determining quadtree coding and the encoding mode of the block.
As described above, the conventional HEVC encoding apparatus actually calculates rate-distortion cost based on the results of encoding and decoding after the performance of both encoding and decoding has been completed. The conventional HEVC encoding apparatus consumes a lot of time in encoding. Further, when a Rate-Distortion Optimized Quantization (RDOQ) method is applied to the HEVC encoding apparatus, the HEVC encoding apparatus performs such a large number of encoding operations that fast encoding for practical use in the real world is actually impossible.
In order to overcome the above-described disadvantages, an HEVC test model, which is reference HEVC software, uses 1) a method for rapidly determining skip and merge, 2) a method for reducing the computational load of Asymmetric Motion Partitioning (AMP), and 3) a method for omitting intra-prediction when a residual signal is small upon performing inter-prediction. However, since these methods basically calculate rate-distortion cost, the additional calculation of rate-distortion cost may be reduced, but there is a limitation on the extent of reduction of the basic encoding computation time.
In relation to technology for performing block encoding using rate-distortion cost, Korean Patent Application Publication No. 2014-0104064 and U.S. Patent Application Publication No. 2014-0146884 are disclosed.